ATA8743-PXQW【PDF 147/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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147

9152BINDCO02/10

ATA8743

An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF

bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.

A start condition interrupt will wake up the processor from all sleep modes.

" Bit 6 USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An

interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag is cleared if a one is written to the USIOIF bit or by read-

ing the USIBR register. Clearing this bit will release the counter overflow hold of SCL in

Two-wire mode.

A counter overflow interrupt will wake up the processor from Idle sleep mode.

" Bit 5 USIPF: Stop Condition Flag

When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected.

The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is

useful when implementing Two-wire bus master arbitration.

" Bit 4 USIDC: Data Output Collision

This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The flag

is only valid when Two-wire mode is used. This signal is useful when implementing Two-wire

bus master arbitration.

" Bits 3..0 USICNT3..0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or

written by the CPU.

The 4-bit counter increments by one for each clock generated either by the external clock edge

detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe

bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation

a special feature is added that allows the clock to be generated by writing to the USITC strobe

bit. This feature is enabled by write a one to the USICLK bit while setting an external clock

source (USICS1 = 1).

Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input

(USCK/SCL) are can still be used by the counter.

23.5.4

USICR USI Control Register

The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,

and clock strobe.

" Bit 7 USISIE: Start Condition Interrupt Enable

Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-

rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be

Bit

0x0D (0x2D)

USISIE

USIOIE

USIWM1

USIWM0

USICS1

USICS0

USICLK

USITC

USICR

Read/Write

R/W

Initial Value

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